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HFBR-57E5APZ multimode small form-factor pluggable transceivers with lc connector and dmi for atm, fddi, fast ethernet and sonet oc-3/sdh stm-1 data sheet description the HFBR-57E5APZ small form-factor pluggable lc trans- ceiver gives the system designer a product to implement fddi/fast ethernet network with dmi and sonet oc-3 (sdh stm-1) physical layers for atm and other services. as an enhancement to the conventional sfp interface defi ned in sff-8074i, the HFBR-57E5APZ is compatible to sff-8472 (digital diagnostic interface for optical trans- ceivers). using the 2-wire serial interface defi ned in the sff-8472 msa, the HFBR-57E5APZ provides real-time information on temperature, led bias current, led average output power and receiver average input power. the interface also adds the ability to monitor the receiver loss of signal (rx_los). transmitter the transmitter contains a 1310 nm ingaasp led. the led is packaged in the optical subassembly of the trans- mitter. it is driven by an integrated circuit which converts diff erential pecl logic signals into an analog led drive current. this current is monitored by the digital diagnostic interface. the transmitter light output power is inferred from this information. receiver the receiver utilizes an ingaas pin photodiode coupled to a transimpedance preamplifi er ic. it is packaged in the optical subassembly of the receiver. the pin/preamplifi er combination is connected to a quantizer ic which provides the fi nal pulse shaping for data output. the data output is diff erential lvpecl. the quantizer ic has a loss of signal (los) detection circuit and has an open collector logic high output signal in the absence of a usable input optical signal. this los output is +3.3 v ttl as per sff-8074i. the pin photodiode average current is monitored by the digital diagnostic interface as a measure for input optical power. features ?? rohs compliant ?? compatible with atm forum uni sonet oc-3 multi- mode fi ber physical layer specifi cation ?? lead free ?? industry standard small form pluggable (sfp) package ?? lc duplex connector optical interface ?? operates with 50/125 ? m and 62.5/125 ? m multimode fi ber ?? compatible with 100base-fx version of ieee802.3u ?? single +3.3 v power supply ?? +3.3 v ttl los output ?? receiver outputs are squelch enabled ?? manufactured in an iso 9001 certifi ed facility ?? -40 c to 85 c temperature range ?? bail de-latch ?? hot plug capability applications ?? factory automation at fast ethernet speeds ?? fast ethernet networking over multimode fi ber ?? oc-3 sfp transceivers are designed for atm lan and wan applications such as: C atm switches and routers C sonet/sdh switch infrastructure ?? multimode fi ber atm backbone links
2 20 v ee t 19 td? 18 td+ 17 v ee t 16 v cc t 15 v cc r 14 v ee r 13 rd+ 12 rd? 11 v ee r top of board 1v ee t 2 nc** 3 txdisable 4 mod-def(2) 5 mod-def(1) 6 mod-def(0) 7nc 8 los 9v ee r 10 v ee r bottom of board (as viewed through top of board) ** connect to internal ground figure 2. connection diagram of module printed circuit board. loss of signal the loss of signal (los) output indicates that the optical input signal to the receiver does not meet the minimum detectable level for fddi and oc-3 compliance. when los is high, it indicates a link failure such as a disconnected or broken fi ber connection or a malfunctioning transmitter. module package the transceiver package is compliant with the small form pluggable (sfp) msa with the lc duplex connector option. the hot-pluggable capability of the sfp package allows the module to be installed at any time C even with the host system operating and on-line. this permits the system to be confi gured or maintained without system downtime. the HFBR-57E5APZ requires a 3.3 v dc power supply for optimal performance. module diagrams figure 1 illustrates the major functional components of the HFBR-57E5APZ . the connection diagram of the module is shown in figure 2. figures 5 and 7 depict the external confi guration and dimensions of the module. installation the HFBR-57E5APZ can be installed in or removed from any multisource agreement (msa) compliant small form pluggable port regardless of whether the host equipment is operating or not. the module is simply inserted, electri- cal interface fi rst, under fi nger pressure. controlled hot- plugging is ensured by design and by 3-stage pin sequencing at the electrical interface. the module housing makes initial contact with the host board emi shield mitigating potential damage due to electro-static discharge (esd). the 3-stage pin contact sequencing figure 1. transceiver functional diagram involves (1) ground, (2) power, and then (3) signal pins making contact with the host board surface mount connector in that order. this printed circuit board card edge connector is depicted in figure 2. digital diagnostic interface and serial identifi cation the 2-wire serial interface is based on the atmel at24c01a series eeprom protocol. conventional eeprom memory (bytes 0-255 at memory address 0xa0) is organized in compliance with sff-8074i. as an enhancement the HFBR-57E5APZ is also compatible to sff-8472. this enhancement off ers digital diagnostic information at bytes 0-255 at memory address 0xa2. in addition to monitoring of the led drive current and photodiode current, the interface also monitors the trans- mitter supply voltage and temperature. the transmitter voltage supply must be provided for the digital diagnostic interface to operate. li g ht f rom fi b e r li g ht t o fi b e r p h o t o - d ete c t or r e c eive r amp lifi ca ti on & q uan tiz a ti on rd + ( r e c eive da t a ) rd C ( r e c eive da t a ) r x l oss o f s i gna l le d t ransm itte r le d dr ive r tx_ d i sab le t d + (t ransm it da t a ) t d C (t ransm it da t a ) tx_f au lt ele c t r i ca l i n te r f ac e mod - d ef 2 ( sda ) mod - d ef1 ( sc l) mod - d ef 0 con t ro lle r & m e mor y op ti ca l i n te r f ac e
3 table 1. regulator compliance feature test method performance electrostatic discharge (esd) to the electrical pins mil-std-883c hbm 2 kv electrostatic discharge (esd) to the duplex lc receptacle variation of iec 61000-4-2 typically withstand at least 25 kv without damage when the lc connector receptacle is contacted by a human body model probe. electromagnetic interference (emi) cenelec cen55022 class b system margins are dependant on customer board and chassis design. immunity variation of iec 61000-4-3 typically shows a negligible eff ect from a 10 v/m fi eld swept from 80 to 450 mhz applied to the transceiver without a chassis enclosure. eye safety ael class 1 en60825-1 (+a11) compliant per avago testing under single fault conditions. rohs compliance reference to eu rohs directive 2002/95/ec functional data i/o the HFBR-57E5APZ fi ber-optic transceiver is designed to accept industry standard diff erential signals. the trans- ceiver provides an ac-coupled, internally terminated data interface. coupling capacitors have been included within the module to reduce the number of components on the customers board. figure 3 depicts the recommended interface circuitry. regulator compliance see table 1 for transceiver regulatory compliance perfor- mance. the overall equipment design will determine the certifi cation level. the transceiver performance is off ered as a fi gure of merit to assist the designer. electrostatic discharge (esd) there are two conditions where immunity to esd damage is important. table 1 documents our immunity to both these conditions. the fi rst condition is static discharge to the transceiver when handling it. for example when the transceiver is inserted into the transceiver port. to protect the trans- ceiver, it is important to use normal esd handling proce- dures. these precautions include grounded wrist straps, workbenches, and fl oor maps in esd controlled areas. the esd sensitivity of the HFBR-57E5APZ is compatible with typical industry production environments. the second condition is static discharge to the exterior of the host equipment chassis after installation. to the extent that the duplex lc optical interface is exposed to the outside of the host equipment chassis, it may be subject to system-level esd events. the esd performance of HFBR-57E5APZ exceeds typical industry standards. immunity equipment hosting the HFBR-57E5APZ will be subjected to radio-frequency electromagnetic fi elds in some en- vironments. these transceivers have good immunity to such fi elds due to their shielded design. electromagnetic interference (emi) most equipment designs utilizing these high-speed trans- ceivers from avago will be required to meet the require- ments of cenelec en55022. the metal housing design and shielded design of the HFBR-57E5APZ transceiver minimize the emi challenge facing the host equipment designer. the transceivers provide superior emi performance. eye safety these transceivers provide class 1 eye safety by design. avago has tested the transceiver design for compliance with the requirements listed in table 1 under normal operating conditions and under a single fault condition. flammability the HFBR-57E5APZ transceiver housing is made of metal and high strength, heat resistant, chemically resistant and ul-94v-0 fl ame retardant plastic. shipping container 10 transceivers are packaged in one shipping container designed to protect it from mechanical and esd damage during shipment or storage.
4 figure 4. msa required power supply fi lter v cc t 0.1 f 0.1 f 10 f 1 h 1 h 0.1 f 10 f 3.3 v sfp module v cc r host board note: inductors must have less than 1 ohm series resistance per msa. note: please refer to the phy or serdes suppliers recommendation regarding the interface between HFBR-57E5APZ and serdes. (components in dotted line box show lvpecl-termination at vcc=3.3v for rx only) figure 3. recommended connection circuitry tx dis pro t oco l i c r x_l os sda sc l modu le d ete c t se r des so + so C s i+ s iC mod _ d ef1 mod _ d ef 2 mod _ d ef 0 3.3 v 4.7 k to 1 0 k : 4.7 k to 1 0 k : 4.7 k to 1 0 k : r x_ gnd 3.3 v 0. 1 p f 50 50 con t ro lle r amp lifie r & q uan tiz a ti on le d dr ive r & sa fety c i rcu it r y 1 0 k : hf br - 57 e 5ap z vcc r r x_l os rd C rd + 1 p h 1 p h 0. 1 p f vcct 0. 1 p f 1 0 p f 3.3 v t d C t d + 50 50 tx_ gnd 1 50 : 0. 1 p f 0. 1 p f 0. 1 p f 1 0 p f 0. 1 p f 4.7 k : to 1 0 k : 1 00 : 1 30 : 83 : 83 : 1 30 : 3.3 v
5 table 2. pin description pin name function/description msa notes 1v ee t transmitter ground 2nc nc 1 3 tx disable transmitter disable C module disables on high or open 4 mod-def2 module defi nition 2 C two wire serial id interface 2 5 mod-def1 module defi nition 1 C two wire serial id interface 2 6 mod-def0 module defi nition 0 C grounded in module 2 7nc nc 8 los loss of signal C high indicates loss of signal 3 9v ee r receiver ground 10 v ee r receiver ground 4 11 v ee r receiver ground 4 12 rd- inverse received data out 13 rd+ received data out 14 v ee r receiver ground 15 v cc r receiver power 3.3 v 10% 5 16 v cc t transmitter power 3.3 v 10% 5 17 v ee t transmitter ground 18 td+ transmitter data in 6 19 td- inverse transmitter data in 6 20 v ee t transmitter ground notes: 1. pin 2 is connected to internal ground. 2. mod-def 0, 1, 2 are the module defi nition pins. they should be pulled up with a 4.7 k ? to 10 k ? resistor on the host board to a supply less than v cc t + 0.3 v or v cc r + 0.3 v. in order to use this interface, supply 3.3 v to v cc t. mod-def 0 is grounded by the module to indicate that the module is present. mod-def 1 is the clock line of the two-wire serial interface. mod-def 2 is the data line of the two-wire serial interface. 3. los (loss of signal) is an open collector/drain output which should be pulled up with an externally with a 4.7 k ? to 10 k ? resistor on the host board to a supply less than v cc t, r + 0.3 v. when high, this output indicates that the received optical power is below the worst case receiver sensitivity (as defi ned by the standard in use). in the low state, the output will be pulled to a voltage less than 0.8 v. 4. rd-/+: these are the diff erential receiver outputs. they are ac-coupled to 100 diff erential lines which should be terminated with 100 ? diff erential at the serdes. ac-coupling is present inside the module and is thus not required on the host board. 5. v cc r and v cc t are the receiver and transmitter power supplies. they are defi ned as 2.97 v to 3.63 v at the sfp connector pin. 6. td-/+: these are the diff erential transmitter inputs. they are ac-coupled diff erential lines with 100 ? diff erential termination inside the module. ac-coupling is present inside the module and is thus not required on the host board.
6 table 3. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. limits apply to each parameter in isolation, all other parameters having values within the recommended operation conditions. it should not be assumed that limiting values of more than one parameter can be applied to the products at the same time. exposure to the absolute maximum ratings for extended periods can adversely aff ect device reliability. parameter symbol min max unit notes storage temperature t s -40 +100 c ? supply voltage v cc -0.5 3.63 v ? data input voltage v i -0.5 vcc v ? table 4. recommended operating conditions all the data in this specifi cation refers to the operating conditions above and over lifetime unless otherwise stated. parameter symbol min typ max unit notes case operating temperature t c -40 +85 c note 1, 2 supply voltage v cc 3.0 3.30 3.6 v data output load r l 100 ? diff erential signalling rate (fast ethernet) b 125 mbd 4b/5b. note 3 singalling rate (oc-3) b 155.52 mbd notes: 1. the case temperature is measured at the surface of the topside (see fi gure 5 module drawing) using a thermocouple connected to the housing. 2. electrical and optical specifi cations of the product are guaranteed across recommended case operating t emperature range only. 3. ethernet auto-negotiation pulses are not supported. table 5. transmitter electrical characteristics parameter symbol min typ max unit notes supply current i cc 60 140 ma note 5 power dissipation p diss 200 500 mw diff erential input voltage v diff 0.5 0.8 1.8 v peak-to-peak input diff erential impedance r in 100 ? note 6 transmitter disable (tx disable) high v ih 2.0 3.5 v transmitter disable (tx disable) low v il 0 0.8 v notes: 5. typical value is valid for room temperature and 3.3 v. 6. connected directly to tx data input pins. ac coupling from pins into driver ic. table 6. receiver electrical characteristics parameter symbol min typ max unit notes supply current i cc 67 100 ma power dissipation p diss 220 360 mw data output: receiver diff erential output voltage (rd+/-) |v oh -v ol | 0.4 2.0 v notes 7, 8 data output rise time (10%-90%) t r 2.20 ns data output fall time (10%-90%) t f 2.20 ns loss of signal output voltage C low losv ol 0.8 v loss of signal output voltage C high losv oh 2.0 v notes: 7. diff erential output voltage is internally ac-coupled but requires an external load termination (100 ? diff erential). the low and high voltages are measured under this load condition. 8. data and data-bar outputs are squelched at los assert levels.
7 table 7. transmitter optical characteristics parameter symbol min typ max unit notes output optical power 62.5/125 ? m na = 0.275 fiber po -20.0 -17.0 -14.0 dbm average power, note 1 output optical power 50/125 ? m na = 0.20 fiber po -23.5 -20.0 -14.0 dbm average power, note 1 extinction ratio er 10 db central wavelength ? c 1270 1308 1380 nm spectral width C fwhm ?? 147 nm optical rise time (10%-90%) t r 0.6 1.0 3.0 ns optical fall time (10%-90%) t f 0.6 1.0 3.0 ns duty cycle distortion contributed by the transmitter dcd 0.60 ns note 2, 3 data dependent jitter contributed by the transmitter ddj 0.60 ns note 3 random jitter contributed by the transmitter rj 0.69 ns note 3, peak-to-peak 0.1 0.52 ns note 4, peak-to-peak, oc-3 systematic jitter contributed by the transmitter oc-3 sj 0.25 1.2 ns note 5, peak-to-peak, oc-3 transmitter disable (high) po(off ) -45 dbm notes: 1. these optical power values are measured over the specifi ed operating voltage and tempera ture ranges. the average power value can be converted to a peak power value by adding 3 db. 2. duty cycle distortion contributed by the transmitter is measured at the 50% threshold of the optical output signal. 3. characterized with prbs2 7 -1 pattern. 4. random jitter contributed by the transmitter is specifi ed with a 155.52 mbd (77.76 mhz square-wave) input signal. 5. systematic jitter contributed by the transmitter is defi ned as the combination of duty cycle distortion and data dependent jitter. it's measured with 50% threshold using 2^23-1 prbs input pattern at 155.52 mbd. table 8. receiver optical and electrical characteristics parameter symbol min typ max unit notes optical input power p in -31.0 -14.0 dbm note 6, average power -31.0 -14.0 note 6, 9, average power, oc-3 operating wavelength ? r 1270 1380 nm duty cycle distortion contributed by the receiver dcd 0.4 ns note 7, 8 data dependent jitter contributed by the receiver ddj 1.0 ns note 8 random jitter contributed by the receiver rj 0.1 2.14 ns note 8, peak-to-peak 0.1 1.91 ns note 10, peak-to-peak, oc-3 systematic jitter contributed by the receiver oc-3 sj 0.16 1.2 ns note 11, peak-to-peak, oc-3 loss of signal C de-asserted p d -32.0 dbm average loss of signal C asserted p a -45 dbm average loss of signal C hysteresis p a C p d 0.5 1.8 db notes: 6. this specifi cation is intended to indicate the performance of the receiver section of the transceiver when optical input power signal char acteristics are present per the following defi nitions: ?? over the specifi ed operating tempera ture and voltage ranges ?? bit error rate (ber) is better than or equal to 1 x 10 -10 ?? transmitter is operating to simulate any cross-talk present bet ween the transmitter and receiver sections of the transceiver. ?? fiber: 62.5/125 ? m, na = 0.275; or 50/125 ? m, na = 0.20 7. duty cycle distortion contributed by the receiver is measured at the 50% threshold of the electrical output signal. 8. characterized with prbs2 7 -1 pattern. 9. measured per 50/125 ? m (na = 0.2) fi ber with a 155.52 mbd (77.76 mhz square-wave) input pattern. 10. random jitter contributed by the receiver is specifi ed with a 155.52 mbd (77.76 mhz square-wave) input signal. 11. systematic jitter contributed by the receiver is defi nied as the combination of duty cycle distortion and data dependent jitter. it's measured with 50% threshold using 2^23-1 prbs input pattern at 155.52 mbd.
8 table 9. transceiver diagnostics timing characteristics parameter symbol min max unit notes hardware txdis assert time t_off 10 ? s note 1, figure 8 hardware txdis de-assert time t_on 10 ? s note 2, figure 8 time to initialize t_init 300 ms note 3, figure 8 hardware los assert time t_sd_on 100 ? s note 4 hardware los de-assert time t_sd_off 350 ? s note 5 software tx_disable assert time t_off _soft 100 ms note 6 software tx_disable de-assert time t_on_soft 100 ms note 7 software rx_los assert time t_loss_on_soft 100 ms note 8 software rx_los de-assert time t_loss_off _soft 100 ms note 9 analog parameter data ready t_data 1000 ms note 10 serial hardware ready t_serial 300 ms note 11 write cycle time t_write 10 ms note 12 serial id clock rate f_serial_clock 400 khz notes: 1. time from rising edge of txdis to when the optical output falls below 10% of nominal. 2. time from falling edge of txdis to when the modulated optical output rises above 90% of nominal. 3. time from power on or falling edge of txdis to when the modulated optical output rises above 90% of nominal. 4. time from valid optical signal to sd assertion. 5. time from loss of optical signal to sd de-assertion. 6. time from two-wire interface assertion of tx_disable (a2h, byte 110, bit 6) to when the optical output falls below 10% of no minal. measured from falling clock edge after stop bit of write transaction. 7. time from two-wire interface de-assertion of tx_disable (a2h, byte 110, bit 6) to when the modulated optical output rises ab ove 90% of nominal. 8. time for two-wire interface assertion of rx_los (a2h, byte 110, bit 1) from loss of optical signal. 9. time for two-wire interface de-assertion of rx_los (a2h, byte 110, bit 1) from presence of valid optical signal. 10. from power on to data ready bit asserted (a2h, byte 110, bit 0). data ready indicates analog monitoring circuitry is functi onal. 11. time from power on until module is ready for data transmission over the serial bus (reads or writes over a0h and a2h). 12. time from stop bit to completion of a 1-8 byte write command.
9 table 10. transceiver digital diagnostic monitor (read time sense) characteristics. parameter symbol max units notes transceiver internal temperature accuracy t int 3.0 c temperature is measured internal to the transceiver. valid from -40c to +85c case temperature. the temperature reference point is located in the center of the module and is typically 5 to 10 degrees hotter than the module case temperature. transceiver internal supply voltage accuracy v int 0.1 v supply voltage is measured internal to the transceiver and can, with less accuracy, be correlated to voltage at the sfp vcc pin. valid over 3.3 v 10%. transmitter led dc bias current accuracy i int 10 % i int is better than 10% value. transmitter average optical power accuracy p t 3.0 db transmitter power is inferred from the led bias current. received average optical input power accuracy p r 3.0 db coupled from a 62.5/125 ? m fi ber. t_init: txdis negated t_init: txdis asserted t_ o ? & t_ o n: txdis asserted then negated t_sd_ o n & t_sd_ o ? t_init optical signal loss of signal occurance of loss t_sd_ o ? t_sd_ o n txdis transmitted signal t_ o ? t_ o n transmitter signal txdis tx, rx v cc > 2.97v t_init transmitter signal txdis tx, rx v cc > 2.97v figure 5. timing diagrams
10 table 11. eeprom serial id memory contents C address a0h byte # decimal hex ascii description byte # decimal hex ascii description 0 03 sfp transceiver 37 00 104 3817 2 07 lc connector 39 6a 300 4048h 400 4146f 5 01 oc3 42 42 b 6 20 100base-fx compliance 43 52 r 700 442d- 800 45355 900 46377 10 00 47 45 e 11 02 4b/5b encoding [1] 48 35 5 12 01 100mbits/s [2] 49 41 a 13 00 50 50 p 14 00 51 5a z 15 00 52 20 16 c8 53 20 17 c8 54 20 18 00 55 20 19 00 56 20 20 41 a 57 20 21 56 v 58 20 22 41 a 59 20 23 47 g 60 05 note 3 24 4f o 61 1e note 3 25 20 62 00 26 20 63 note 4 27 20 64 00 28 20 65 12 tx disable and los implemented. 29 20 66 00 30 20 67 00 31 20 68 - 83 note 5 32 20 84 - 91 note 6 33 20 92 68 digital diagnostics implemented. internally calibrated. average rx power. 34 20 93 d0 alarm warnings, softtx_disable and soft rx_los implemented. 35 20 94 03 includes functionality described in rev 10.2 of sff-8472. 36 00 95 note 4 96 - 127 00 note 7 notes: 1. also supports sonet oc3 encoding code. 2. also supports 155 mbaud for sonet oc3. 3. led wavelength is represented in 16 unsigned bits. the hex representation of 1310 (nm) is 0x051e. 4. address 63 is the checksum for bytes 0-62 and address 95 is the checksum for bytes 64-94. they are calculated (per sff-8472) and stored prior to product shipment. 5. address 68-83 specify a unique module serial number. 6. address 84-91 specify the date code. 7. address 96-127 is vendor specifi c.
11 table 12. eeprom serial id memory contents - enhanced features (address a2h) byte # decimal notes byte # decimal notes byte # decimal notes 0 temp h alarm msb [1] 26 tx power l alarm msb [4] 104 real time rx power msb [5] 1 temp h alarm lsb [1] 27 tx power l alarm lsb [4] 105 real time rx power lsb [5] 2 temp l alarm msb [1] 28 tx power h warning msb [4] 106 reserved 3 temp l alarm lsb [1] 29 tx power h warning lsb [4] 107 reserved 4 temp h warning msb [1] 30 tx power l warning msb [4] 108 reserved 5 temp h warning lsb [1] 31 tx power l warning lsb [4] 109 reserved 6 temp l warning msb [1] 32 rx power h alarm msb [5] 110 status/control C see table 7 temp l warning lsb [1] 33 rx power h alarm lsb [5] 111 reserved 8 vcc h alarm msb [2] 34 rx power l alarm msb [5] 112 flag bits C see table 9 vcc h alarm lsb [2] 35 rx power l alarm lsb [5] 113 flag bits C see table 10 vcc l alarm msb [2] 36 rx power h warning msb [5] 114 reserved 11 vcc l alarm lsb [2] 37 rx power h warning lsb [5] 115 reserved 12 vcc h warning msb [2] 38 rx power l warning msb [5] 116 flag bits C see table 13 vcc h warning lsb [2] 39 rx power l warning lsb [5] 117 flag bits C see table 14 vcc l warning msb [2] 40-55 reserved 118-127 reserved 15 vcc l warning lsb [2] 56-94 external calibration constants [6] 128-247 customer writable 16 tx bias h alarm msb [3] 95 checksum for bytes 0-94 [7] 248-255 vendor specifi c 17 tx bias h alarm lsb [3] 96 real time temperature msb [1] 18 tx bias l alarm msb [3] 97 real time temperature lsb [1] 19 tx bias l alarm lsb [3] 98 real time vcc msb [2] 20 tx bias h warning msb [3] 99 real time vcc lsb [2] 21 tx bias h warning lsb [3] 100 real time tx bias msb [3] 22 tx bias l warning msb [3] 101 real time tx bias lsb [3] 23 tx bias l warning lsb [3] 102 real time tx power msb [4] 24 tx power h alarm msb [4] 103 real time tx power lsb [4] 25 tx power h alarm lsb [4] notes: 1. temperature (temp) is decoded as a 16 bit sig ned twos complement integer in increments of 1/256c. 2. supply voltage (vcc) is decoded as a 16 bit unsigned integer in increments of 100 ? v. 3. tx bias current (tx bias) is decoded as a 16 bit unsigned integer in increments of 2 ? a. 4. transmitted average optical power (tx pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 ? w. 5. received average optical power (rx pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 ? w. 6. bytes 56-94 are not intended for use with HFBR-57E5APZ, but have been set to default values per sff-8472. 7. byte 95 is a checksum calculated (per sff-8472) and stored prior to product shipment.
12 table 13. eeprom serial id memory contents C soft commands (address a2h, byte 110). bit # status/control name description notes 7 tx_disable state digital state of soft tx_disable 6 soft tx_disable read/write bit for changing digital state of tx_disable function 5 reserved 4 reserved 3 reserved 2 reserved 1 rx_los state digital state of sfp rx_los output pin (1 = rx_los asserted) 0 data ready (bar) indicates transceiver is powered and real time sense data is ready (0 = ready) table 14. eeprom serial id memory contents C alarms and warnings (address a2h, bytes 112, 113, 116, 117) byte bit flag bit name description 112 7 temp high alarm set when transceiver internal temperature exceeds high alarm threshold. 6 temp low alarm set when transceiver internal temperature exceeds low alarm threshold. 5 vcc high alarm set when transceiver internal supply voltage exceeds high alarm threshold. 4 vcc low alarm set when transceiver internal supply voltage exceeds low alarm threshold. 3 tx bias high alarm set when transceiver led bias exceeds high alarm threshold. 2 tx bias low alarm set when transceiver led bias exceeds low alarm threshold. 1 tx power high alarm set when transmitted average optical power exceeds high alarm threshold. 0 tx power low alarm set when transmitted average optical power exceeds low alarm threshold. 113 7 rx power high alarm set when received average optical power exceeds high alarm threshold. 6 rx power low alarm set when received average optical power exceeds low alarm threshold. 0-5 reserved 116 7 temp high warning set when transceiver internal temperature exceeds high warning threshold. 6 temp low warning set when transceiver internal temperature exceeds low warning threshold. 5 vcc high warning set when transceiver internal supply voltage exceeds high warning threshold. 4 vcc low warning set when transceiver internal supply voltage exceeds low warning threshold. 3 tx bias high warning set when transceiver led bias exceeds high warning threshold. 2 tx bias low warning set when transceiver led bias exceeds low warning threshold. 1 tx power high warning set when transmitted average optical power exceeds high warning threshold. 0 tx power low warning set when transmitted average optical power exceeds low warning threshold. 117 7 rx power high warning set when received average optical power exceeds high warning threshold. 6 rx power low warning set when received average optical power exceeds low warning threshold. 0-5 reserved
13 table 15. settings of alarm and warning thresholds tx power [dbm] rx power [dbm] transceiver temperature [c] supply voltage [v] tx bias current [ma] high alarm -10 -10 110 3.6 120 low alarm -23 -33 -45 2.8 10 high warning -12 -12 95 3.5 110 low warning -22 -32 -42 3 15 figure 6. module drawing 13.80.1 [0.5410.004] 2.60 [0.10] 55.20.2 [2.170.01] 13.40.1 [0.5280.004] yyww c o unt r y o f o r igin device shown with dust cap and bail wire delatch 6.250.05 [0.2460.002] tx rx dimensions are in millimeters (inches) 8.50.1 [0.3350.004] front edge of sfp transceiver cage 0.7max. uncompressed [0.028] 13.00.2 [0.5120.008] 6.6 [0.261] 13.50 [0.53] area for process plug 14.8max. uncompressed [0.583] t c ase refe r en c e p o int
14 figure 7. sfp host board mechanical layout 2x 1.7 20x 0.5 0.03 0.9 2 0.005 typ. 0.06 l s as b 10.53 11.93 20 10 11 pin 1 20 10 11 pin 1 0.8 typ. 10.93 9.6 2x 1.55 0.05 3.2 5 legend 1. pads and vias are chassis ground 2. thr ough holes, plating optional 3. hatched area denotes component and trace keepout (except chassis ground) 4. area denotes component keepout (traces allowed) dimensions are in millimeters 4 3 2 1 1 26.8 5 11x 2.0 10 3x 41.3 42.3 b 10x ? 1.05 0.01 16.25 ref . 14.25 11.08 8.58 5.68 2.0 11x 11.93 9.6 4.8 8.48 a 3.68 see det ail 1 9x 0.95 0.05 2.5 7.1 7.2 2.5 10 3x 34.5 16.25 min. pitch y x detail 1 pcb edge ? 0.1 l s as b 0.06 l s as b ? 0.1 l x s a ? 0.1 y x s ? 0.85 0.05 ? 0.1 a s x l
[.600.004] dimensions are in millimeters [inches]. 15.250.1 [.640.004] 16.250.1min pitch [.410.004] 10.40.1 [.39] to pcb 10ref [.020.004] below pcb 0.40.1 [.39] 9.8max [.49] 12.4ref [.05] below pcb 1.15ref [1.64.02] 41.730.5 [.14.01] 3.50.3 [.07.04] 1.70.9 [.59] 15max area for process plug t c ase reference point pcb msa-specified be z el be z el cage assembly figure 8. sfp assembly drawing for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. av02-2146en - july 16, 2012

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